This disclosure relates generally to integrated circuits, and more particularly, to memory cells containing thyristors. Exemplary memory cells comprise gated lateral thyristor-containing random access memory (GLTRAM) cells incorporated into TFT constructions. Such constructions can be formed over a versatile substrate base.
SOI technology differs from traditional bulk semiconductor technologies in that the active semiconductor material of SOI technologies is typically much thinner than that utilized in bulk technologies. The active semiconductor material of SOI technologies will typically be formed as a thin film over an insulating material (typically oxide), with exemplary thicknesses of the semiconductor film being less than or equal to 2000 xc3x85. In contrast, bulk semiconductor material will typically have a thickness of at least about 200 microns. The thin semiconductor of SOI technology can allow higher performance and lower power consumption to be achieved in integrated circuits than can be achieved with similar circuits utilizing bulk materials.
An exemplary integrated circuit device that can be formed utilizing SOI technologies is a so-called thin film transistor (TFT), with the term xe2x80x9cthin filmxe2x80x9d referring to the thin semiconductor film of the SOI construction. In particular aspects, the semiconductor material of the SOI construction can be silicon, and in such aspects the TFTs can be fabricated using recrystallized amorphous silicon or polycrystalline silicon. The silicon can be supported by an electrically insulative material (such as silicon dioxide), which in turn is supported by an appropriate substrate. Exemplary substrate materials include glass, bulk silicon and metal-oxides (such as, for example, Al2O3). If the semiconductor material comprises silicon, the term SOI is occasionally utilized to refer to a silicon-on-insulator construction, rather than the more general concept of a semiconductor-on-insulator construction. However, it is to be understood that in the context of this disclosure the term SOI refers to semiconductor-on-insulator constructions. Accordingly, the semiconductor material of an SOI construction referred to in the context of this disclosure can comprise other semiconductive materials in addition to, or alternatively to, silicon; including, for example, germanium.
A problem associated with conventional TFT constructions is that grain boundaries and defects can limit carrier mobilities. Accordingly, carrier mobilities are frequently nearly an order of magnitude lower than they would be in bulk semiconductor devices. High voltage (and therefore high power consumption), and large areas are utilized for the TFTs, and the TFTs exhibit limited performance. TFTs thus have limited commercial application and currently are utilized primarily for large area electronics.
Various efforts have been made to improve carrier mobility of TFTs. Some improvement is obtained for devices in which silicon is the semiconductor material by utilizing a thermal anneal for grain growth following silicon ion implantation and hydrogen passivation of grain boundaries (see, for example, Yamauchi, N. et al., xe2x80x9cDrastically Improved Performance in Poly-Si TFTs with Channel Dimensions Comparable to Grain Sizexe2x80x9d, IEDM Tech. Digest, 1989, pp. 353-356). Improvements have also been made in devices in which a combination of silicon and germanium is the semiconductor material by optimizing the germanium and hydrogen content of silicon/germanium films (see, for example, King, T. J. et al, xe2x80x9cA Low-Temperature ( less than =550xc2x0 C.) Silicon-Germanium MOS TFT Technology for Large-Area Electronicsxe2x80x9d, IEDM Tech. Digest, 1991, pp. 567-570).
Investigations have shown that nucleation, direction of solidification, and grain growth of silicon crystals can be controlled selectively and preferentially by excimer laser annealing, as well as by lateral scanning continuous wave laser irradiation/anneal for recrystallization (see, for example, Kuriyama, H. et al., xe2x80x9cHigh Mobility Poly-Si TFT by a New Excimer Laser Annealing Method for Large Area Electronicsxe2x80x9d, IEDM Tech. Digest, 1991, pp. 563-566; Jeon, J. H. et al., xe2x80x9cA New Poly-Si TFT with Selectively Doped Channel Fabricated by Novel Excimer Laser Annealingxe2x80x9d, IEDM Tech. Digest, 2000, pp. 213-216; Kim, C. H. et al., xe2x80x9cA New High -Performance Poly-Si TFT by Simple Excimer Laser Annealing on Selectively Floating a Si Layerxe2x80x9d, IEDM Tech. Digest, 2001, pp. 753-756; Hara, A. et al, xe2x80x9cSelective Single-Crystalline-Silicon Growth at the Pre-Defined Active Regions of TFTs on a Glass by a Scanning CW Layer Irradiationxe2x80x9d, IEDM Tech. Digest, 2000, pp. 209-212; and Hara, A. et al., xe2x80x9cHigh Performance Poly-Si TFTs on a Glass by a Stable Scanning CW Laser Lateral Crystallizationxe2x80x9d, IEDM Tech. Digest, 2001, pp. 747-750). Such techniques have allowed relatively defect-free large crystals to be grown, with resulting TFTs shown to exhibit carrier mobility over 300 cm2/N-second.
Another technique which has shown promise for improving carrier mobility is metal-induced lateral recrystallization (MILC), which can be utilized in conjunction with an appropriate high temperature anneal (see, for example, Jagar, S. et al., xe2x80x9cSingle Grain TFT with SOI CMOS Performance Formed by Metal-Induced-Lateral-Crystallizationxe2x80x9d, IEDM Tech. Digest, 1999, p. 293-296; and Gu, J. et al., xe2x80x9cHigh Performance Sub-100 nm Si TFT by Pattern-Controlled Crystallization of Thin Channel Layer and High Temperature Annealingxe2x80x9d, DRC Conference Digest, 2002, pp. 49-50). A suitable post-recrystallization anneal for improving the film quality within silicon recrystallized by MILC is accomplished by exposing recrystallized material to a temperature of from about 850xc2x0 C. to about 900xc2x0 C. under an inert ambient (with a suitable ambient comprising, for example, N2). MILC can allow nearly single crystal silicon grains to be formed in predefined amorphous-silicon islands for device channel regions. Nickel-induced-lateral-recrystallization can allow device properties to approach those of single crystal silicon.
The carrier mobility of a transistor channel region can be significantly enhanced if the channel region is made of a semiconductor material having a strained crystalline lattice (such as, for example, a silicon/germanium material having a strained lattice, or a silicon material having a strained lattice) formed over a semiconductor material having a relaxed lattice (such as, for example, a silicon/germanium material having a relaxed crystalline lattice). (See, for example, Rim, K. et al., xe2x80x9cStrained Si NMOSFETs for High Performance CMOS Technologyxe2x80x9d, VLSI Tech. Digest, 2001, p. 59-60; Cheng, Z. et al., xe2x80x9cSiGe-On-Insulator (SGOI) Substrate Preparation and MOSFET Fabrication for Electron Mobility Evaluationxe2x80x9d 2001 IEEE SOI Conference Digest, Oct. 2001, pp. 13-14; Huang, L. J. et al., xe2x80x9cCarrier Mobility Enhancement in Strained Si-on-Insulator Fabricated by Wafer Bondingxe2x80x9d, VLSI Tech. Digest, 2001, pp. 57-58; and Mizuno, T. et al., xe2x80x9cHigh Performance CMOS Operation of Strained-SOI MOSFETs Using Thin Film SiGe-on-Insulator Substratexe2x80x9d, VLSI Tech. Digest, 2002, p. 106-107.)
The terms xe2x80x9crelaxed crystalline latticexe2x80x9d and xe2x80x9cstrained crystalline latticexe2x80x9d are utilized to refer to crystalline lattices which are within a defined lattice configuration for the semiconductor material, or perturbed from the defined lattice configuration, respectively. In applications in which the relaxed lattice material comprises silicon/germanium having a germanium concentration of from 10% to 60%, mobility enhancements of 110% for electrons and 60-80% for holes can be accomplished by utilizing a strained lattice material in combination with the relaxed lattice material (see for example, Rim, K. et al., xe2x80x9cCharacteristics and Device Design of Sub-100 nm Strained SiN and PMOSFETsxe2x80x9d, VLSI Tech. Digest, 2002, 00. 98-99; and Huang, L. J. et al., xe2x80x9cCarrier Mobility Enhancement in Strained Si-on-Insulator Fabricated by Wafer Bondingxe2x80x9d, VLSI Tech. Digest, 2001, pp. 57-58).
Performance enhancements of standard field effect transistor devices are becoming limited with progressive lithographic scaling in conventional applications. Accordingly, strained-lattice-channeled-field effect transistors on relaxed silicon/germanium offers an opportunity to enhance device performance beyond that achieved through conventional lithographic scaling. IBM recently announced the world""s fastest communications chip following the approach of utilizing a strained crystalline lattice over a relaxed crystalline lattice (see, for example, xe2x80x9cIBM Builds World""s Fastest Communications Microchipxe2x80x9d, Reuters U.S. Company News, Feb. 25, 2002; and Markoff, J., xe2x80x9cIBM Circuits are Now Faster and Reduce Use of Powerxe2x80x9d, The New York Times, Feb. 25, 2002).
Although various techniques have been developed for substantially controlling nucleation and grain growth processes of semiconductor materials, grain orientation control is lacking. Further, the post-anneal treatment utilized in conjunction with MILC can be unsuitable in applications in which a low thermal budget is desired. Among the advantages of the invention described below is that such can allow substantial control of crystal grain orientation within a semiconductor material, while lowering thermal budget requirements relative to conventional methods. Additionally, the quality of the grown crystal formed from a semiconductor material can be improved relative to that of conventional methods.
Integrated circuit memory includes dynamic random access memory (DRAM) and static random access memory (SRAM). DRAM cells provide good memory density, but are relatively slow. SRAM cells are faster than DRAM cells, but the area utilized for SRAM cells is large. The large area associated with six-transistor and four-transistor memory cells has limited the design of high-density SRAM devices.
Negative differential resistance (NDR) devices have been used to reduce the number of elements per memory cell. However, NDR devices tend to suffer from problems such as high standby power consumption, high operating voltages, low speeds and complicated fabrication processes. F. Nemati and J. D. Plummer have disclosed a two-device thyristor-based SRAM cell (TRAM) that includes an access transistor and a gate-assisted, vertical thyristor. The disclosed vertical p+/n/p/n+ thyristor is operated in a gate-enhanced switching mode to provide the memory cell with SRAM-like performance and DRAM-like density. The performance of the TRAM cell depends on the turn-off characteristics of the vertical thyristor, and the turn-off characteristics depend on the stored charge and carrier transit time in the p-region of the p+/n/p/n+ thyristor. The turn-off characteristics for the vertical thyristor are improved from milliseconds to five nanoseconds by reverse biasing the thyristor for a write-zero operation and by using a gate to assist with turn-off switching of the thyristor by discharging the stored charge. Even so, the geometry and vertical height of the vertical thyristor""s p-region limits the turn-off characteristics and the associated cell performance of the gate-assisted, vertical thyristor disclosed by Nemati and Plummer. The scalability of the TRAM cell and the ability to control the performance of the TRAM cell are also limited.
It would be desirable to provide improved memory cells that provide DRAM-like density, faster SRAM-like performance, and scalability.
The present invention pertains to SOI constructions comprising at least one memory cell encompassing a transistor and a thyristor. In one aspect, the present invention encompasses a one-device equivalent, gated lateral thyristor-based random access memory (GLTRAM) cell incorporated into a TFT construction. An exemplary memory cell construction includes a crystalline layer comprising silicon and germanium over an electrically insulative material. An access transistor device has an active region extending into the crystalline layer. The entirety of the active region within the crystalline layer is within only a single crystal of the crystalline layer. The transistor device includes a gate, source region and drain region. A thyristor is electrically connected with the source region. The thyristor can be integrated with, and stacked on top of, the access transistor to enhance the density of the memory cell. The geometry of the thyristor can be accurately controlled to provide a lower stored charge volume. Further, the thyristor can be tailored to reduce carrier transit time, which can provide faster performance and improve the gate-assisted turn-off characteristics of the thyristor.
In various aspects, the lateral thyristor can be fabricated using an MILC technique adopted for TFT technology. Accordingly, the GLTRAM cell can be readily scalable with lithography to provide direct scalability with technology generations. In particular embodiments, the stacked lateral thyristor is integrated by raising the source region of the access transistor using a selective epitaxy process. The stacked configuration of the GLTRAM cell can have a footprint less than 8F2, and thus can have a higher density than the TRAM cell. Additionally, the GLTRAM cell can have a low standby power consumption during cell operation.
In one aspect, the invention encompasses a memory device which includes a transistor and a thyristor electrically connected with a source/drain region of the transistor. The transistor has a gate supported by a crystalline layer. The crystalline layer is less than or equal to 2000 Angstroms thick, and comprises a Si/Ge material. The transistor has an active region, and at least a portion of the active region is within the Si/Ge material. The active region within the Si/Ge material is contained within a single crystal of the material.